ASIC Design Flow에서 합성 후 다음 단계인 chip-level physical implementation 을 위한 이론 및 설계 툴을 배운다. Design Planning, Place & Routing, Clock Tree Synthesis 및 optimization 등을 다룬다.
교과목해설(영문)
This course teaches student how to use cad tools for chip-level physical implementation. It includes design planning, placement & routing, clock tree synthesis, and optimization.
